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$Rev:20696$
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00001 # unit test for the cvel task 00002 00003 import os 00004 import numpy 00005 import shutil 00006 from __main__ import default 00007 from tasks import * 00008 from taskinit import * 00009 import unittest 00010 00011 myname = 'test_cvel' 00012 vis_a = 'ngc4826.ms' 00013 vis_b = 'test.ms' 00014 vis_c = 'jupiter6cm.demo-thinned.ms' 00015 vis_d = 'g19_d2usb_targets_line-shortened-thinned.ms' 00016 vis_e = 'evla-highres-sample-thinned.ms' 00017 vis_f = 'test_cvel1.ms' 00018 outfile = 'cvel-output.ms' 00019 00020 def verify_ms(msname, expnumspws, expnumchan, inspw, expchanfreqs=[]): 00021 msg = '' 00022 tb.open(msname+'/SPECTRAL_WINDOW') 00023 nc = tb.getcell("NUM_CHAN", inspw) 00024 nr = tb.nrows() 00025 cf = tb.getcell("CHAN_FREQ", inspw) 00026 tb.close() 00027 tb.open(msname) 00028 dimdata = tb.getcell("FLAG", 0)[0].size 00029 tb.close() 00030 if not (nr==expnumspws): 00031 msg = "Found "+str(nr)+", expected "+str(expnumspws)+" spectral windows in "+msname 00032 return [False,msg] 00033 if not (nc == expnumchan): 00034 msg = "Found "+ str(nc) +", expected "+str(expnumchan)+" channels in spw "+str(inspw)+" in "+msname 00035 return [False,msg] 00036 if not (dimdata == expnumchan): 00037 msg = "Found "+ str(dimdata) +", expected "+str(expnumchan)+" channels in FLAG column in "+msname 00038 return [False,msg] 00039 00040 if not (expchanfreqs==[]): 00041 print "Testing channel frequencies ..." 00042 print cf 00043 print expchanfreqs 00044 if not (expchanfreqs.size == expnumchan): 00045 msg = "Internal error: array of expected channel freqs should have dimension ", expnumchan 00046 return [False,msg] 00047 df = (cf - expchanfreqs)/expchanfreqs 00048 if not (abs(df) < 1E-8).all: 00049 msg = "channel frequencies in spw "+str(inspw)+" differ from expected values by (relative error) "+str(df) 00050 return [False,msg] 00051 00052 return [True,msg] 00053 00054 00055 class cvel_test(unittest.TestCase): 00056 00057 def setUp(self): 00058 default('cvel') 00059 forcereload=False 00060 00061 if(forcereload or not os.path.exists(vis_a)): 00062 shutil.rmtree(vis_a, ignore_errors=True) 00063 importuvfits(fitsfile=os.environ['CASAPATH'].split()[0]+'/data/regression/ngc4826/fitsfiles/ngc4826.ll.fits5', # 10 MB 00064 vis=vis_a) 00065 if(forcereload or not os.path.exists(vis_b)): 00066 shutil.rmtree(vis_b, ignore_errors=True) 00067 os.system('cp -R '+os.environ['CASAPATH'].split()[0]+'/data/regression/fits-import-export/input/test.ms .') # 27 MB 00068 if(forcereload or not os.path.exists(vis_c)): 00069 shutil.rmtree(vis_c, ignore_errors=True) 00070 os.system('cp -R '+os.environ['CASAPATH'].split()[0]+'/data/regression/cvel/input/jupiter6cm.demo-thinned.ms .') # 124 MB 00071 if(forcereload or not os.path.exists(vis_d)): 00072 shutil.rmtree(vis_d, ignore_errors=True) 00073 os.system('cp -R '+os.environ['CASAPATH'].split()[0]+'/data/regression/cvel/input/g19_d2usb_targets_line-shortened-thinned.ms .') # 48 MB 00074 if(forcereload or not os.path.exists(vis_e)): 00075 shutil.rmtree(vis_e, ignore_errors=True) 00076 os.system('cp -R '+os.environ['CASAPATH'].split()[0]+'/data/regression/cvel/input/evla-highres-sample-thinned.ms .') # 74 MB 00077 if(forcereload or not os.path.exists(vis_f)): 00078 shutil.rmtree(vis_f, ignore_errors=True) 00079 os.system('cp -R '+os.environ['CASAPATH'].split()[0]+'/data/regression/unittest/cvel/test_cvel1.ms .') # 39 MB 00080 00081 self.assertTrue(os.path.exists(vis_a)) 00082 self.assertTrue(os.path.exists(vis_b)) 00083 self.assertTrue(os.path.exists(vis_c)) 00084 self.assertTrue(os.path.exists(vis_d)) 00085 self.assertTrue(os.path.exists(vis_e)) 00086 self.assertTrue(os.path.exists(vis_f)) 00087 00088 00089 def tearDown(self): 00090 os.system('rm -rf cvel-output.ms cvel-output.ms.deselected myinput.ms') 00091 pass 00092 00093 def test1(self): 00094 '''Cvel 1: Testing default - expected error''' 00095 myvis = vis_b 00096 os.system('ln -sf ' + myvis + ' myinput.ms') 00097 rval = cvel() 00098 self.assertFalse(rval) 00099 00100 def test2(self): 00101 '''Cvel 2: Only input vis set - expected error''' 00102 myvis = vis_b 00103 os.system('ln -sf ' + myvis + ' myinput.ms') 00104 rval = cvel(vis = 'myinput.ms') 00105 self.assertEqual(rval,None) 00106 00107 def test3(self): 00108 '''Cvel 3: Input and output vis set''' 00109 myvis = vis_b 00110 os.system('ln -sf ' + myvis + ' myinput.ms') 00111 rval = cvel(vis = 'myinput.ms', outputvis = outfile) 00112 self.assertNotEqual(rval,False) 00113 ret = verify_ms(outfile, 1, 64, 0) 00114 self.assertTrue(ret[0],ret[1]) 00115 00116 def test4(self): 00117 '''Cvel 4: I/O vis set, more complex input vis, one field selected''' 00118 myvis = vis_a 00119 os.system('ln -sf ' + myvis + ' myinput.ms') 00120 rval = cvel(vis = 'myinput.ms', outputvis = outfile, field = '1') 00121 self.assertNotEqual(rval,False) 00122 ret = (verify_ms(outfile, 1, 64, 0)) 00123 self.assertTrue(ret[0],ret[1]) 00124 00125 def test5(self): 00126 '''Cvel 5: I/O vis set, more complex input vis, one field selected, passall = True''' 00127 myvis = vis_a 00128 os.system('ln -sf ' + myvis + ' myinput.ms') 00129 rval = cvel( 00130 vis = 'myinput.ms', 00131 outputvis = outfile, 00132 field = '1', 00133 passall = True 00134 ) 00135 self.assertNotEqual(rval,False) 00136 ret = (verify_ms(outfile, 2, 64, 0)) 00137 self.assertTrue(ret[0],ret[1]) 00138 00139 def test6(self): 00140 '''Cvel 6: I/O vis set, more complex input vis, one field selected, one spw selected, passall = True''' 00141 myvis = vis_a 00142 os.system('ln -sf ' + myvis + ' myinput.ms') 00143 rval = cvel( 00144 vis = 'myinput.ms', 00145 outputvis = outfile, 00146 field = '1', 00147 spw = '0', 00148 passall = True 00149 ) 00150 self.assertNotEqual(rval,False) 00151 ret = (verify_ms(outfile, 2, 64, 0)) 00152 self.assertTrue(ret[0],ret[1]) 00153 00154 ## # Tests with more than one spectral window ################### 00155 00156 def test7(self): 00157 '''Cvel 7: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 00158 passall = False''' 00159 myvis = vis_c 00160 os.system('ln -sf ' + myvis + ' myinput.ms') 00161 rval = cvel( 00162 vis = 'myinput.ms', 00163 outputvis = outfile, 00164 field = '12', # select Jupiter 00165 spw = '0,1', # both available SPWs 00166 passall = False 00167 ) 00168 self.assertNotEqual(rval,False) 00169 ret = (verify_ms(outfile, 1, 2, 0)) 00170 self.assertTrue(ret[0],ret[1]) 00171 00172 def test8(self): 00173 '''Cvel 8: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 00174 passall = False, regridding 1''' 00175 myvis = vis_c 00176 os.system('ln -sf ' + myvis + ' myinput.ms') 00177 rval = cvel( 00178 vis = 'myinput.ms', 00179 outputvis = outfile, 00180 field = '11', # select some other field 00181 spw = '0,1', # both available SPWs 00182 passall = False, # regrid 00183 nchan = 1, 00184 width = 2 00185 ) 00186 self.assertNotEqual(rval,False) 00187 ret = (verify_ms(outfile, 1, 1, 0)) 00188 self.assertTrue(ret[0],ret[1]) 00189 00190 def test9(self): 00191 '''Cvel 9: I/O vis set, input vis with two spws, one field selected, 2 spws selected, 00192 passall = False, regridding 2''' 00193 myvis = vis_c 00194 os.system('ln -sf ' + myvis + ' myinput.ms') 00195 rval = cvel( 00196 vis = 'myinput.ms', 00197 outputvis = outfile, 00198 field = '10', 00199 spw = '0,1', 00200 passall = False, 00201 mode='channel', 00202 nchan = 1, 00203 start = 1 00204 ) 00205 self.assertNotEqual(rval,False) 00206 ret = (verify_ms(outfile, 1, 1, 0)) 00207 self.assertTrue(ret[0],ret[1]) 00208 00209 def test10(self): 00210 '''Cvel10: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 3...''' 00211 myvis = vis_c 00212 os.system('ln -sf ' + myvis + ' myinput.ms') 00213 rval = cvel( 00214 vis = 'myinput.ms', 00215 outputvis = outfile, 00216 field = '9', 00217 spw = '0,1', 00218 passall = False, 00219 mode='frequency', 00220 nchan = 1, 00221 start = '4.8351GHz', 00222 width = '50MHz' 00223 ) 00224 self.assertNotEqual(rval,False) 00225 ret = verify_ms(outfile, 1, 1, 0) 00226 self.assertTrue(ret[0],ret[1]) 00227 00228 00229 def test11(self): 00230 '''Cvel 11: I/O vis set, input vis with two spws, one field selected, 00231 2 spws selected, passall = False, regridding 4...''' 00232 myvis = vis_c 00233 os.system('ln -sf ' + myvis + ' myinput.ms') 00234 00235 rval = cvel( 00236 vis = 'myinput.ms', 00237 outputvis = outfile, 00238 field = '10', 00239 spw = '0,1', 00240 passall = False, 00241 mode='channel', 00242 nchan = 1, 00243 start = 1, 00244 outframe = 'lsrk' 00245 ) 00246 self.assertNotEqual(rval,False) 00247 ret = verify_ms(outfile, 1, 1, 0) 00248 self.assertTrue(ret[0],ret[1]) 00249 00250 def test12(self): 00251 '''Cvel 12: Input and output vis set, input vis with two spws, two fields selected, 00252 2 spws selected, passall = False, regridding 5...''' 00253 myvis = vis_c 00254 os.system('ln -sf ' + myvis + ' myinput.ms') 00255 rval = cvel( 00256 vis = 'myinput.ms', 00257 outputvis = outfile, 00258 field = '5,6', 00259 spw = '0,1', 00260 passall = False, 00261 mode='frequency', 00262 nchan = 2, 00263 start = '4.8101 GHz', 00264 width = '50 MHz', 00265 outframe = '' 00266 ) 00267 self.assertNotEqual(rval,False) 00268 ret = verify_ms(outfile, 1, 2, 0) 00269 self.assertTrue(ret[0],ret[1]) 00270 00271 def test13(self): 00272 '''Cvel 13: I/O vis set, input vis with one spws, one field selected, one spws selected, 00273 passall = False, regridding 6...''' 00274 myvis = vis_a 00275 os.system('ln -sf ' + myvis + ' myinput.ms') 00276 rval = cvel( 00277 vis = 'myinput.ms', 00278 outputvis = outfile, 00279 field = '1', 00280 spw = '0', 00281 passall = False, 00282 mode='frequency', 00283 nchan = 2, 00284 start = '115GHz', 00285 width = '3MHz', 00286 outframe = 'BARY', 00287 phasecenter = 1 00288 ) 00289 self.assertNotEqual(rval,False) 00290 ret = verify_ms(outfile, 1, 2, 0) 00291 self.assertTrue(ret[0],ret[1]) 00292 00293 def test14(self): 00294 '''Cvel 14: I/O vis set, input vis with one spws, one field selected, one spws selected, 00295 passall = False, non-existing phase center...''' 00296 myvis = vis_a 00297 os.system('ln -sf ' + myvis + ' myinput.ms') 00298 try: 00299 rval = cvel( 00300 vis = 'myinput.ms', 00301 outputvis = outfile, 00302 field = '1', 00303 spw = '0', 00304 passall = False, 00305 mode='frequency', 00306 nchan = 2, 00307 start = '150GHz', 00308 width = '3MHz', 00309 outframe = 'BARY', 00310 phasecenter = 12 00311 ) 00312 self.assertNotEqual(rval,False) 00313 ret = verify_ms(outfile, 1, 2, 0) 00314 self.assertTrue(ret[0],ret[1]) 00315 except: 00316 print "*** Expected error ***" 00317 00318 def test15(self): 00319 '''Cvel 15: I/O vis set, input vis with two spws, one field selected, 2 spws selected, passall = False, regridding 8...''' 00320 myvis = vis_c 00321 os.system('ln -sf ' + myvis + ' myinput.ms') 00322 rval = cvel( 00323 vis = 'myinput.ms', 00324 outputvis = 'cvel-output.ms', 00325 field = '12', 00326 spw = '0,1', 00327 passall = False, 00328 mode='frequency', 00329 nchan = 1, 00330 start = '4.850GHz', 00331 width = '50MHz', 00332 outframe = '' 00333 ) 00334 self.assertNotEqual(rval,False) 00335 ret = verify_ms(outfile, 1, 1, 0) 00336 self.assertTrue(ret[0],ret[1]) 00337 00338 def test16(self): 00339 '''Cvel 16: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...''' 00340 myvis = vis_a 00341 os.system('ln -sf ' + myvis + ' myinput.ms') 00342 rval = cvel( 00343 vis = 'myinput.ms', 00344 outputvis = outfile, 00345 field = '2,3', 00346 spw = '0', 00347 passall = False, 00348 mode='channel', 00349 nchan = 10, 00350 start = 2, 00351 outframe = 'lsrd', 00352 phasecenter = 2 00353 ) 00354 self.assertNotEqual(rval,False) 00355 ret = verify_ms(outfile, 1, 10, 0) 00356 self.assertTrue(ret[0],ret[1]) 00357 00358 def test17(self): 00359 '''Cvel 17: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...''' 00360 myvis = vis_a 00361 os.system('ln -sf ' + myvis + ' myinput.ms') 00362 rval = cvel( 00363 vis = 'myinput.ms', 00364 outputvis = 'cvel-output.ms', 00365 field = '2,3', 00366 spw = '0', 00367 passall = False, 00368 mode='frequency', 00369 nchan = 10, 00370 start = '114.9527GHz', 00371 width = '3.125MHz', 00372 outframe = 'lsrd', 00373 phasecenter = 2) 00374 self.assertNotEqual(rval,False) 00375 ret = verify_ms(outfile, 1, 10, 0) 00376 self.assertTrue(ret[0],ret[1]) 00377 00378 def test18(self): 00379 '''Cvel 18: I/O vis set, input vis with one spw, two fields selected, passall = False, regridding 9...''' 00380 myvis = vis_a 00381 os.system('ln -sf ' + myvis + ' myinput.ms') 00382 rval = cvel( 00383 vis = 'myinput.ms', 00384 outputvis = outfile, 00385 field = '2,3', 00386 spw = '0', 00387 passall = False, 00388 mode='frequency', 00389 nchan = 10, 00390 start = '114.9527GHz', 00391 width = '3.125MHz', 00392 outframe = 'lsrd', 00393 phasecenter = 'J2000 12h56m43.88s +21d41m00.1s' 00394 ) 00395 self.assertNotEqual(rval,False) 00396 ret = verify_ms(outfile, 1, 10, 0) 00397 self.assertTrue(ret[0],ret[1]) 00398 00399 def test19(self): 00400 '''Cvel 19: SMA input MS, 24 spws to combine, channel mode, 10 output channels''' 00401 myvis = vis_d 00402 os.system('ln -sf ' + myvis + ' myinput.ms') 00403 rval = cvel( 00404 vis = 'myinput.ms', 00405 outputvis = outfile, 00406 mode='channel', 00407 nchan = 10, 00408 start = 100, 00409 width = 2, 00410 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00411 ) 00412 self.assertNotEqual(rval,False) 00413 ret = verify_ms(outfile, 1, 10, 0) 00414 self.assertTrue(ret[0],ret[1]) 00415 00416 def test20(self): 00417 '''Cvel 20: SMA input MS, 24 spws to combine, channel mode, 111 output channels''' 00418 myvis = vis_d 00419 os.system('ln -sf ' + myvis + ' myinput.ms') 00420 rval = cvel( 00421 vis = 'myinput.ms', 00422 outputvis = outfile, 00423 mode='channel', 00424 nchan = 111, 00425 start = 201, 00426 width = 3, 00427 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00428 ) 00429 self.assertNotEqual(rval,False) 00430 ret = verify_ms(outfile, 1, 111, 0) 00431 self.assertTrue(ret[0],ret[1]) 00432 00433 def test21(self): 00434 '''Cvel 21: SMA input MS, 24 spws to combine, frequency mode, 21 output channels''' 00435 myvis = vis_d 00436 os.system('ln -sf ' + myvis + ' myinput.ms') 00437 rval = cvel( 00438 vis = 'myinput.ms', 00439 outputvis = outfile, 00440 mode='frequency', 00441 nchan = 21, 00442 start = '229587.0MHz', 00443 width = '1600kHz', 00444 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00445 ) 00446 self.assertNotEqual(rval,False) 00447 ret = verify_ms(outfile, 1, 21, 0) 00448 self.assertTrue(ret[0],ret[1]) 00449 00450 def test22(self): 00451 '''Cvel 22: SMA input MS, 24 spws to combine, frequency mode, 210 output channels, negative width''' 00452 myvis = vis_d 00453 os.system('ln -sf ' + myvis + ' myinput.ms') 00454 rval = cvel( 00455 vis = 'myinput.ms', 00456 outputvis = outfile, 00457 mode='frequency', 00458 nchan = 210, 00459 start = '229588.0MHz', 00460 width = '-2400kHz', 00461 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00462 ) 00463 self.assertNotEqual(rval,False) 00464 ret = verify_ms(outfile, 1, 210, 0) 00465 self.assertTrue(ret[0],ret[1]) 00466 os.system('mv '+outfile+' xxx.ms') 00467 00468 def test23(self): 00469 '''Cvel 23: SMA input MS, 24 spws to combine, radio velocity mode, 30 output channels''' 00470 myvis = vis_d 00471 os.system('ln -sf ' + myvis + ' myinput.ms') 00472 vrad = (220398.676E6 - 229586E6)/220398.676E6 * 2.99792E8 00473 vwidth = ((220398.676E6 - 229586E6+1600E3)/220398.676E6 * 2.99792E8) - vrad 00474 vrad = vrad-vwidth/2. 00475 rval = cvel( 00476 vis = 'myinput.ms', 00477 outputvis = outfile, 00478 mode='velocity', 00479 nchan = 30, 00480 restfreq = '220398.676MHz', 00481 start = str(vrad)+'m/s', 00482 width = str(vwidth)+'m/s', 00483 phasecenter = "J2000 18h25m56.09 -12d04m28.20", 00484 veltype = 'radio' 00485 ) 00486 self.assertNotEqual(rval,False) 00487 ret = verify_ms(outfile, 1, 30, 0) 00488 self.assertTrue(ret[0],ret[1]) 00489 00490 def test24(self): 00491 '''Cvel 24: SMA input MS, 24 spws to combine, radio velocity mode, 35 output channels''' 00492 myvis = vis_d 00493 os.system('ln -sf ' + myvis + ' myinput.ms') 00494 vrad = (220398.676E6 - 229586E6)/220398.676E6 * 2.99792E8 00495 vwidth = ((220398.676E6 - 229586E6+3200E3)/220398.676E6 * 2.99792E8) - vrad 00496 vrad = vrad-vwidth/2. 00497 rval = cvel( 00498 vis = 'myinput.ms', 00499 outputvis = outfile, 00500 mode='velocity', 00501 nchan = 35, 00502 restfreq = '220398.676MHz', 00503 start = str(vrad)+'m/s', 00504 width = str(vwidth)+'m/s', 00505 phasecenter = "J2000 18h25m56.09 -12d04m28.20", 00506 veltype = 'radio' 00507 ) 00508 self.assertNotEqual(rval,False) 00509 ret = verify_ms(outfile, 1, 35, 0) 00510 self.assertTrue(ret[0],ret[1]) 00511 00512 def test25(self): 00513 '''Cvel 25: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels''' 00514 myvis = vis_d 00515 os.system('ln -sf ' + myvis + ' myinput.ms') 00516 lambda0 = 2.99792E8/220398.676E6 00517 lambda1 = 2.99792E8/229586E6 00518 lambda2 = 2.99792E8/(229586E6+1600E3) 00519 vopt = (lambda1-lambda0)/lambda0 * 2.99792E8 00520 vwidth = vopt - (lambda2-lambda0)/lambda0 * 2.99792E8 00521 vopt = vopt-vwidth/2. 00522 rval = cvel( 00523 vis = 'myinput.ms', 00524 outputvis = outfile, 00525 mode='velocity', 00526 nchan = 40, 00527 restfreq = '220398.676MHz', 00528 start = str(vopt)+'m/s', 00529 width = str(vwidth)+'m/s', 00530 phasecenter = "J2000 18h25m56.09 -12d04m28.20", 00531 veltype = 'optical' 00532 ) 00533 self.assertNotEqual(rval,False) 00534 ret = verify_ms(outfile, 1, 40, 0) 00535 self.assertTrue(ret[0],ret[1]) 00536 00537 def test26(self): 00538 '''Cvel 26: SMA input MS, 24 spws to combine, optical velocity mode, 40 output channels''' 00539 myvis = vis_d 00540 os.system('ln -sf ' + myvis + ' myinput.ms') 00541 lambda0 = 2.99792E8/220398.676E6 00542 lambda1 = 2.99792E8/229586E6 00543 vopt = (lambda1-lambda0)/lambda0 * 2.99792E8 00544 lambda2 = 2.99792E8/(229586E6+1200E3) 00545 vwidth = vopt - (lambda2-lambda0)/lambda0 * 2.99792E8 00546 vopt = vopt-vwidth/2. 00547 rval = cvel( 00548 vis = 'myinput.ms', 00549 outputvis = outfile, 00550 mode='velocity', 00551 nchan = 41, 00552 restfreq = '220398.676MHz', 00553 start = str(vopt)+'m/s', 00554 width = str(vwidth)+'m/s', 00555 phasecenter = "J2000 18h25m56.09 -12d04m28.20", 00556 veltype = 'optical' 00557 ) 00558 self.assertNotEqual(rval,False) 00559 ret = verify_ms(outfile, 1, 41, 0) 00560 self.assertTrue(ret[0],ret[1]) 00561 00562 def test27(self): 00563 '''Cvel 27: SMA input MS, 24 spws to combine, scratch columns, no regridding''' 00564 myvis = vis_d 00565 os.system('ln -sf ' + myvis + ' myinput.ms') 00566 # no regrid 00567 rval = cvel( 00568 vis = 'myinput.ms', 00569 outputvis = outfile 00570 ) 00571 self.assertNotEqual(rval,False) 00572 ret = verify_ms(outfile, 1, 2440, 0) 00573 self.assertTrue(ret[0],ret[1]) 00574 00575 def test28(self): 00576 '''Cvel 28: SMA input MS, 24 spws to combine, scratch columns, channel mode, 30 channels''' 00577 myvis = vis_d 00578 os.system('ln -sf ' + myvis + ' myinput.ms') 00579 rval = cvel( 00580 vis = 'myinput.ms', 00581 outputvis = outfile, 00582 mode="channel", 00583 start=1500, 00584 width=2, 00585 nchan=30 00586 ) 00587 self.assertNotEqual(rval,False) 00588 ret = verify_ms(outfile, 1, 30, 0) 00589 self.assertTrue(ret[0],ret[1]) 00590 00591 def test29(self): 00592 '''Cvel 29: SMA input MS, 24 spws to combine, scratch columns, channel mode, 31 channels''' 00593 myvis = vis_d 00594 os.system('ln -sf ' + myvis + ' myinput.ms') 00595 rval = cvel( 00596 vis = 'myinput.ms', 00597 outputvis = outfile, 00598 mode="channel", 00599 start=1500, 00600 width=2, 00601 nchan=31 00602 ) 00603 self.assertNotEqual(rval,False) 00604 ret = verify_ms(outfile, 1, 31, 0) 00605 self.assertTrue(ret[0],ret[1]) 00606 00607 def test30(self): 00608 '''Cvel 30: SMA input MS, 24 spws to combine, scratch columns, mode channel_b, no regridding''' 00609 myvis = vis_d 00610 os.system('ln -sf ' + myvis + ' myinput.ms') 00611 rval = cvel( 00612 vis = 'myinput.ms', 00613 outputvis = outfile, 00614 mode="channel_b" 00615 ) 00616 00617 self.assertNotEqual(rval,False) 00618 ret = verify_ms(outfile, 1, 2425, 0) 00619 self.assertTrue(ret[0],ret[1]) 00620 00621 def test31(self): 00622 '''Cvel 31: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo''' 00623 myvis = vis_d 00624 os.system('ln -sf ' + myvis + ' myinput.ms') 00625 rval = cvel( 00626 vis = 'myinput.ms', 00627 outputvis = outfile, 00628 mode="channel", 00629 outframe = "BARY", 00630 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00631 ) 00632 self.assertNotEqual(rval,False) 00633 ret = verify_ms(outfile, 1, 2440, 0) 00634 self.assertTrue(ret[0],ret[1]) 00635 00636 def test32(self): 00637 '''Cvel 32: SMA input MS, 24 spws to combine, scratch columns, mode channel, frame trafo, Hanning smoothing''' 00638 myvis = vis_d 00639 os.system('ln -sf ' + myvis + ' myinput.ms') 00640 rval = cvel( 00641 vis = 'myinput.ms', 00642 outputvis = outfile, 00643 mode="channel", 00644 outframe = "BARY", 00645 phasecenter = "J2000 18h25m56.09 -12d04m28.20", 00646 hanning = True 00647 ) 00648 self.assertNotEqual(rval,False) 00649 ret = verify_ms(outfile, 1, 2440, 0) 00650 self.assertTrue(ret[0],ret[1]) 00651 00652 def test33(self): 00653 '''Cvel 33: SMA input MS, 1 spw, scratch columns, mode channel, no trafo, Hanning smoothing''' 00654 myvis = vis_d 00655 os.system('ln -sf ' + myvis + ' myinput.ms') 00656 rval = cvel( 00657 vis = 'myinput.ms', 00658 spw='1', 00659 outputvis = outfile, 00660 mode="channel", 00661 outframe = "", 00662 hanning = True 00663 ) 00664 self.assertNotEqual(rval,False) 00665 ret = verify_ms(outfile, 1, 128, 0) 00666 self.assertTrue(ret[0],ret[1]) 00667 00668 def test34(self): 00669 '''Cvel 34: EVLA high-res input MS, 2 spws to combine''' 00670 myvis = vis_e 00671 os.system('ln -sf ' + myvis + ' myinput.ms') 00672 rval = cvel( 00673 vis = 'myinput.ms', 00674 outputvis = outfile, 00675 mode = 'velocity', 00676 restfreq = '6035.092MHz' 00677 ) 00678 self.assertNotEqual(rval,False) 00679 ret = verify_ms(outfile, 1, 260, 0) 00680 self.assertTrue(ret[0],ret[1]) 00681 00682 def test35(self): 00683 '''Cvel 35: test effect of sign of width parameter: channel mode, width positive''' 00684 myvis = vis_b 00685 os.system('ln -sf ' + myvis + ' myinput.ms') 00686 tb.open('myinput.ms/SPECTRAL_WINDOW') 00687 a = tb.getcell('CHAN_FREQ') 00688 b = numpy.array([a[1], a[2], a[3]]) 00689 tb.close() 00690 00691 rval = cvel( 00692 vis = 'myinput.ms', 00693 outputvis = outfile, 00694 nchan = 3, 00695 start = 1, 00696 width=1 00697 ) 00698 self.assertNotEqual(rval,False) 00699 ret = verify_ms(outfile, 1, 3, 0, b) 00700 self.assertTrue(ret[0],ret[1]) 00701 00702 def test36(self): 00703 '''Cvel 36: test effect of sign of width parameter: channel mode, width negative''' 00704 myvis = vis_b 00705 os.system('ln -sf ' + myvis + ' myinput.ms') 00706 tb.open('myinput.ms/SPECTRAL_WINDOW') 00707 a = tb.getcell('CHAN_FREQ') 00708 b = numpy.array([a[1], a[2], a[3]]) 00709 tb.close() 00710 00711 rval = cvel( 00712 vis = 'myinput.ms', 00713 outputvis = outfile, 00714 nchan = 3, 00715 start = 3, 00716 width=-1 00717 ) 00718 self.assertNotEqual(rval,False) 00719 ret = verify_ms(outfile, 1, 3, 0, b) 00720 self.assertTrue(ret[0],ret[1]) 00721 00722 def test37(self): 00723 '''Cvel 37: test effect of sign of width parameter: freq mode, width positive''' 00724 myvis = vis_b 00725 os.system('ln -sf ' + myvis + ' myinput.ms') 00726 tb.open('myinput.ms/SPECTRAL_WINDOW') 00727 a = tb.getcell('CHAN_FREQ') 00728 b = numpy.array([a[1], a[2], a[3]]) 00729 tb.close() 00730 00731 rval = cvel( 00732 vis = 'myinput.ms', 00733 outputvis = outfile, 00734 mode = 'frequency', 00735 nchan = 3, 00736 start = str(a[1])+'Hz', 00737 width=str(a[2]-a[1])+'Hz' 00738 ) 00739 self.assertNotEqual(rval,False) 00740 ret = verify_ms(outfile, 1, 3, 0, b) 00741 self.assertTrue(ret[0],ret[1]) 00742 00743 def test38(self): 00744 '''Cvel 38: test effect of sign of width parameter: freq mode, width negative''' 00745 myvis = vis_b 00746 os.system('ln -sf ' + myvis + ' myinput.ms') 00747 tb.open('myinput.ms/SPECTRAL_WINDOW') 00748 a = tb.getcell('CHAN_FREQ') 00749 b = numpy.array([a[1], a[2], a[3]]) 00750 tb.close() 00751 00752 rval = cvel( 00753 vis = 'myinput.ms', 00754 outputvis = outfile, 00755 mode = 'frequency', 00756 nchan = 3, 00757 start = str(a[3])+'Hz', 00758 width='-'+str(a[2]-a[1])+'Hz' 00759 ) 00760 self.assertNotEqual(rval,False) 00761 ret = verify_ms(outfile, 1, 3, 0, b) 00762 self.assertTrue(ret[0],ret[1]) 00763 00764 def test39(self): 00765 '''Cvel 39: test effect of sign of width parameter: radio velocity mode, width positive''' 00766 myvis = vis_b 00767 os.system('ln -sf ' + myvis + ' myinput.ms') 00768 tb.open('myinput.ms/SPECTRAL_WINDOW') 00769 a = tb.getcell('CHAN_FREQ') 00770 c = qa.constants('c')['value'] 00771 tb.close() 00772 00773 restf = a[0] 00774 bv1 = c * (restf-a[5])/restf 00775 bv2 = c * (restf-a[4])/restf 00776 wv = abs(bv2-bv1) 00777 b = numpy.array([a[3], a[4], a[5]]) 00778 rval = cvel( 00779 vis = 'myinput.ms', 00780 outputvis = outfile, 00781 mode = 'velocity', 00782 veltype = 'radio', 00783 nchan = 3, 00784 start = str(bv1)+'m/s', 00785 width=str(wv)+'m/s', 00786 restfreq=str(restf)+'Hz' 00787 ) 00788 self.assertNotEqual(rval,False) 00789 ret = verify_ms(outfile, 1, 3, 0, b) 00790 self.assertTrue(ret[0],ret[1]) 00791 00792 def test40(self): 00793 '''Cvel 40: test effect of sign of width parameter: radio velocity mode, width negative''' 00794 myvis = vis_b 00795 os.system('ln -sf ' + myvis + ' myinput.ms') 00796 tb.open('myinput.ms/SPECTRAL_WINDOW') 00797 a = tb.getcell('CHAN_FREQ') 00798 c = qa.constants('c')['value'] 00799 tb.close() 00800 00801 restf = a[0] 00802 bv1 = c * (restf-a[3])/restf 00803 bv2 = c * (restf-a[4])/restf 00804 wv = abs(bv2-bv1) 00805 b = numpy.array([a[3], a[4], a[5]]) 00806 rval = cvel( 00807 vis = 'myinput.ms', 00808 outputvis = outfile, 00809 mode = 'velocity', 00810 veltype = 'radio', 00811 nchan = 3, 00812 start = str(bv1)+'m/s', 00813 width="-"+str(wv)+'m/s', 00814 restfreq=str(restf)+'Hz' 00815 ) 00816 self.assertNotEqual(rval,False) 00817 ret = verify_ms(outfile, 1, 3, 0, b) 00818 self.assertTrue(ret[0],ret[1]) 00819 00820 def test41(self): 00821 '''Cvel 41: test effect of sign of width parameter: optical velocity mode, width positive''' 00822 myvis = vis_b 00823 os.system('ln -sf ' + myvis + ' myinput.ms') 00824 tb.open('myinput.ms/SPECTRAL_WINDOW') 00825 a = tb.getcell('CHAN_FREQ') 00826 c = qa.constants('c')['value'] 00827 tb.close() 00828 00829 restf = a[0] 00830 bv1 = c * (restf-a[5])/a[5] 00831 bv2 = c * (restf-a[4])/a[4] 00832 wv = abs(bv2-bv1+1.) 00833 bv2 = bv1 + wv 00834 bv3 = bv2 + wv 00835 a4 = restf/(bv2/c+1.) 00836 a3 = restf/(bv3/c+1.) 00837 b = numpy.array([a3, a4, a[5]]) 00838 rval = cvel( 00839 vis = 'myinput.ms', 00840 outputvis = outfile, 00841 mode = 'velocity', 00842 veltype = 'optical', 00843 nchan = 3, 00844 start = str(bv1)+'m/s', 00845 width=str(wv)+'m/s', 00846 restfreq=str(restf)+'Hz' 00847 ) 00848 self.assertNotEqual(rval,False) 00849 ret = verify_ms(outfile, 1, 3, 0, b) 00850 self.assertTrue(ret[0],ret[1]) 00851 00852 def test42(self): 00853 '''Cvel 42: test effect of sign of width parameter: optical velocity mode, width negative''' 00854 myvis = vis_b 00855 os.system('ln -sf ' + myvis + ' myinput.ms') 00856 tb.open('myinput.ms/SPECTRAL_WINDOW') 00857 a = tb.getcell('CHAN_FREQ') 00858 c = qa.constants('c')['value'] 00859 tb.close() 00860 00861 restf = a[0] 00862 bv1 = c * (restf-a[5])/a[5] 00863 bv2 = c * (restf-a[4])/a[4] 00864 wv = abs(bv2-bv1+1.) 00865 bv2 = bv1 + wv 00866 bv3 = bv2 + wv 00867 a4 = restf/(bv2/c+1.) 00868 a3 = restf/(bv3/c+1.) 00869 b = numpy.array([a3, a4, a[5]]) 00870 rval = cvel( 00871 vis = 'myinput.ms', 00872 outputvis = outfile, 00873 mode = 'velocity', 00874 veltype = 'optical', 00875 nchan = 3, 00876 start = str(bv3)+'m/s', 00877 width='-'+str(wv)+'m/s', 00878 restfreq=str(restf)+'Hz' 00879 ) 00880 self.assertNotEqual(rval,False) 00881 ret = verify_ms(outfile, 1, 3, 0, b) 00882 self.assertTrue(ret[0],ret[1]) 00883 00884 def test43(self): 00885 '''Cvel 43: SMA input MS, 1 spw, channel mode, nchan not set''' 00886 myvis = vis_d 00887 os.system('ln -sf ' + myvis + ' myinput.ms') 00888 rval = cvel( 00889 vis = 'myinput.ms', 00890 outputvis = outfile, 00891 mode='channel', 00892 spw='1', 00893 start = 98, 00894 width = 3, 00895 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00896 ) 00897 self.assertNotEqual(rval,False) 00898 ret = verify_ms(outfile, 1, 10, 0) 00899 self.assertTrue(ret[0],ret[1]) 00900 00901 def test44(self): 00902 '''Cvel 44: SMA input MS, 2 spws to combine, channel mode, nchan not set''' 00903 myvis = vis_d 00904 os.system('ln -sf ' + myvis + ' myinput.ms') 00905 rval = cvel( 00906 vis = 'myinput.ms', 00907 outputvis = outfile, 00908 mode='channel', 00909 spw='1,15', 00910 start = 198, 00911 width = 3, 00912 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00913 ) 00914 self.assertNotEqual(rval,False) 00915 ret = verify_ms(outfile, 1, 10, 0) 00916 self.assertTrue(ret[0],ret[1]) 00917 00918 def test45(self): 00919 '''Cvel 45: SMA input MS, 1 spw, channel mode, nchan not set, negative width''' 00920 myvis = vis_d 00921 os.system('ln -sf ' + myvis + ' myinput.ms') 00922 rval = cvel( 00923 vis = 'myinput.ms', 00924 outputvis = outfile, 00925 mode='channel', 00926 spw='1', 00927 start = 29, 00928 width = -3, 00929 phasecenter = "J2000 18h25m56.09 -12d04m28.20" 00930 ) 00931 self.assertNotEqual(rval,False) 00932 ret = verify_ms(outfile, 1, 10, 0) 00933 self.assertTrue(ret[0],ret[1]) 00934 00935 def test46(self): 00936 '''Cvel 46: SMA input MS with descending freq, 24 spws, nchan=100''' 00937 myvis = vis_f 00938 os.system('ln -sf ' + myvis + ' myinput.ms') 00939 rval = cvel( 00940 vis = 'myinput.ms', 00941 outputvis = outfile, 00942 mode='channel', 00943 spw='', 00944 start = 29, 00945 nchan = 100 00946 ) 00947 self.assertNotEqual(rval,False) 00948 ret = verify_ms(outfile, 1, 100, 0) 00949 self.assertTrue(ret[0],ret[1]) 00950 00951 def test47(self): 00952 '''Cvel 47: SMA input MS with descending freq, 1 spw, nchan not set''' 00953 myvis = vis_f 00954 os.system('ln -sf ' + myvis + ' myinput.ms') 00955 rval = cvel( 00956 vis = 'myinput.ms', 00957 outputvis = outfile, 00958 mode='channel', 00959 spw='10', 00960 start = 98, 00961 width=3 00962 ) 00963 self.assertNotEqual(rval,False) 00964 ret = verify_ms(outfile, 1, 10, 0) 00965 self.assertTrue(ret[0],ret[1]) 00966 00967 def test48(self): 00968 '''Cvel 48: test fftshift regridding: channel mode, width positive''' 00969 myvis = vis_b 00970 os.system('ln -sf ' + myvis + ' myinput.ms') 00971 tb.open('myinput.ms/SPECTRAL_WINDOW') 00972 a = tb.getcell('CHAN_FREQ') 00973 b = numpy.array([a[1], a[2], a[3]]) 00974 tb.close() 00975 00976 rval = cvel( 00977 vis = 'myinput.ms', 00978 outputvis = outfile, 00979 nchan = 3, 00980 start = 1, 00981 width = 1, 00982 interpolation = 'fftshift' 00983 ) 00984 self.assertNotEqual(rval,False) 00985 ret = verify_ms(outfile, 1, 3, 0, b) 00986 self.assertTrue(ret[0],ret[1]) 00987 00988 def test49(self): 00989 '''Cvel 49: vopt mode with fftshift, expected error ...''' 00990 myvis = vis_b 00991 os.system('ln -sf ' + myvis + ' myinput.ms') 00992 try: 00993 rval = cvel( 00994 vis = 'myinput.ms', 00995 outputvis = outfile, 00996 mode='velocity', 00997 veltype='optical', 00998 restfreq = '220398.676MHz', 00999 outframe = 'BARY', 01000 interpolation = 'fftshift' 01001 ) 01002 self.assertNotEqual(rval,False) 01003 ret = verify_ms(outfile, 1, 2, 0) 01004 self.assertTrue(ret[0],ret[1]) 01005 except: 01006 print "*** Expected error ***" 01007 01008 def test50(self): 01009 '''Cvel 50: test fftshift regridding: channel mode, width positive''' 01010 myvis = vis_d 01011 os.system('ln -sf ' + myvis + ' myinput.ms') 01012 01013 # get reference values by running cvel with linear interpol 01014 cvel( 01015 vis = 'myinput.ms', 01016 outputvis = outfile, 01017 spw = '0,1', 01018 nchan = 150, 01019 start = 10, 01020 width = 1, 01021 interpolation = 'linear', 01022 outframe = 'CMB' 01023 ) 01024 01025 tb.open(outfile+'/SPECTRAL_WINDOW') 01026 a = tb.getcell('CHAN_FREQ') 01027 b = numpy.array(a) 01028 tb.close() 01029 01030 shutil.rmtree(outfile, ignore_errors=True) 01031 01032 rval = cvel( 01033 vis = 'myinput.ms', 01034 outputvis = outfile, 01035 spw = '0,1', 01036 nchan = 150, 01037 start = 10, 01038 width = 1, 01039 # interpolation = 'linear', 01040 interpolation = 'fftshift', 01041 outframe = 'CMB' 01042 ) 01043 01044 self.assertNotEqual(rval,False) 01045 ret = verify_ms(outfile, 1, 150, 0, b) 01046 self.assertTrue(ret[0],ret[1]) 01047 01048 def test51(self): 01049 '''Cvel 51: test fftshift regridding: frequency mode, width positive''' 01050 myvis = vis_d 01051 os.system('ln -sf ' + myvis + ' myinput.ms') 01052 01053 # get reference values by running cvel with linear interpol 01054 cvel( 01055 mode = 'frequency', 01056 vis = 'myinput.ms', 01057 outputvis = outfile, 01058 spw = '0,1', 01059 nchan = 150, 01060 interpolation = 'linear', 01061 outframe = 'BARY' 01062 ) 01063 01064 tb.open(outfile+'/SPECTRAL_WINDOW') 01065 a = tb.getcell('CHAN_FREQ') 01066 b = numpy.array(a) 01067 tb.close() 01068 01069 shutil.rmtree(outfile, ignore_errors=True) 01070 01071 rval = cvel( 01072 mode = 'frequency', 01073 vis = 'myinput.ms', 01074 outputvis = outfile, 01075 spw = '0,1', 01076 nchan = 150, 01077 interpolation = 'fftshift', 01078 outframe = 'BARY' 01079 ) 01080 01081 self.assertNotEqual(rval,False) 01082 ret = verify_ms(outfile, 1, 150, 0, b) 01083 self.assertTrue(ret[0],ret[1]) 01084 01085 def test52(self): 01086 '''Cvel 52: test fftshift regridding: radio velocity mode, width positive''' 01087 myvis = vis_d 01088 os.system('ln -sf ' + myvis + ' myinput.ms') 01089 01090 # get reference values by running cvel with linear interpol 01091 cvel( 01092 mode = 'velocity', 01093 veltype = 'radio', 01094 restfreq = '220398.676MHz', 01095 vis = 'myinput.ms', 01096 outputvis = outfile, 01097 spw = '0,1', 01098 nchan = 150, 01099 interpolation = 'linear', 01100 outframe = 'CMB' 01101 ) 01102 01103 tb.open(outfile+'/SPECTRAL_WINDOW') 01104 a = tb.getcell('CHAN_FREQ') 01105 b = numpy.array(a) 01106 tb.close() 01107 01108 shutil.rmtree(outfile, ignore_errors=True) 01109 01110 rval = cvel( 01111 mode = 'velocity', 01112 veltype = 'radio', 01113 restfreq = '220398.676MHz', 01114 vis = 'myinput.ms', 01115 outputvis = outfile, 01116 spw = '0,1', 01117 nchan = 150, 01118 interpolation = 'fftshift', 01119 outframe = 'CMB' 01120 ) 01121 01122 self.assertNotEqual(rval,False) 01123 ret = verify_ms(outfile, 1, 150, 0, b) 01124 self.assertTrue(ret[0],ret[1]) 01125 01126 01127 class cleanup(unittest.TestCase): 01128 def setUp(self): 01129 pass 01130 01131 def tearDown(self): 01132 # It will ignore errors in case files don't exist 01133 shutil.rmtree(vis_a,ignore_errors=True) 01134 shutil.rmtree(vis_b,ignore_errors=True) 01135 shutil.rmtree(vis_c,ignore_errors=True) 01136 shutil.rmtree(vis_d,ignore_errors=True) 01137 shutil.rmtree(vis_e,ignore_errors=True) 01138 shutil.rmtree(vis_f,ignore_errors=True) 01139 01140 def test_cleanup(self): 01141 '''Cvel: Cleanup''' 01142 pass 01143 01144 01145 01146 def suite(): 01147 return [cvel_test,cleanup] 01148
1.8.0
